Product Overview
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Wafer Bumping
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Wafer Level CSP
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BGA/LGA
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Flip Chip CSP
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QFN/DFN
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Flip Chip QFN/DFN/SOP/TSOT
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P-DIP
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TO&SOT
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SOIC / SSOP / TSSOP
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SOJ&PLCC
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QFP / LQFP / TQFP

 

Wafer Bumping

Overview

Greatek support 8” (200mm) wafer level bumping process, Greatek offers RDL only for wire bonding assembly, SnAg solder bump and Cu pillar bump for flip chip assembly, WLCSP for chip scale package.

RDL: Re-distribution line to link the same I/O pad function or re-routing pad location for assembly.

SnAg solder bump: High bump density, small bump pitch and bump size.

Cu pillar bump: High bump density with fine pitch, shorter interconnect length, high electrical performance.

WLCSP: An integrated circuit at wafer level, instead of the traditional assembly package, reduced package size, and enhanced thermal conduction characteristics

Wafer bumping capability and experience

 

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